1. Field of the Invention
The present invention relates to a liquid crystal display panel using polycrystalline silicon, and more particularly, to a liquid crystal display panel and a method of fabricating thereof that is capable of enhancing the crystallization efficiency of an active layer and reducing the number of fabricating processes.
2. Discussion of the Related Art
Generally, liquid crystal displays (LCD) control the light transmittance of liquid crystal cells in accordance with video signals, thereby displaying pictures corresponding to the video signals on a liquid crystal display panel where the liquid crystal cells are arranged in a matrix form. In this case, a thin film transistor (TFT) is typically used as a switching device for the liquid crystal cells.
The semiconductor layer of such a thin film transistor is made of either amorphous silicon or polycrystalline silicon. Amorphous silicon TFTs have an advantage in that they have relatively better uniformity and stable property. However, the amorphous silicon TFTs also have a disadvantage in that response speed is slow because the carrier mobility of amorphous silicon is low. Thus, it is difficult to apply such amorphous silicon TFTs to a high resolution display panel requiring a rapid response speed or to a driving device for a gate driver and a data driver. In contrast, because the carrier mobility of polycrystalline silicon is high, polycrystalline silicon TFTs have drawn attention for the applications of liquid crystal display panels with a high resolution and peripheral driving circuits mounted in the display panels.
FIG. 1 and FIG. 2 are a plan view and a sectional view of a related art liquid crystal display panel having such a polycrystalline silicon TFT.
Referring to FIGS. 1 and 2, the liquid crystal display panel having the thin film transistor includes a gate line 2, a data line 4 crossing the gate line 2 with an insulating film 12 therebetween, a TFT 30 provided at a crossing of the gate line 2 and the data line 4, and a pixel electrode 22 provided in a pixel area defined by the crossing of the gate line 2 and the data line 4.
The gate line 2 applies a gate signal to a gate electrode 6 of the TFT 30. The data line 4 applies a pixel signal to the pixel electrode 22 via a drain electrode 10 of the TFT 30.
The TFT 30 includes the gate electrode 6 connected to the gate line 2, a source electrode 8 connected to the data line 4 and a drain electrode 10 connected, via a contact hole 20 passing through a passivation film 18, to the pixel electrode 22.
The gate electrode 6 is formed on a buffer film 16 so as to overlap a channel area 14C of the active layer, with the gate insulating film 12 between the gate electrode 6 and the channel area 14C. The source electrode 8 is formed to be insulated from the gate electrode 6 with the gate insulating film 12 therebetween and to be directly connected to a source area 14S of the active layer. The drain electrode 10 is formed to be insulated from the gate electrode 6 with the gate insulating film 12 therebetween and to be connected to a drain area 14D of the active layer. Different ions, depending on the location of the active layer 14 and type of the TFT 30, are injected into the active layer 14. In other words, if the TFT 30 has an N channel, at least one of n+ and n− ions is injected into the active layer. The active layer to which the n− ions are injected becomes a Lightly Doped Drain (LDD) area, which is generally used to reduce the off-current of the TFT 30. The active layer into which the n+ ions are injected becomes the source area and the drain area, and the active layer into which the n+ and n− ions are not injected become the channel area. If the TFT 30 has a P channel, p+ ions are injected into the active layer. While the active layer into which the p+ ions are injected becomes the source and the drain areas, the active layer into which the p+ ions are not injected become the channel area.
Such a TFT 30 responds to a scanning pulse applied from the gate line 2, to thereby allow a video signal, that is, a pixel signal applied from the data line 4, to be charged in a liquid crystal cell. As a result, the liquid crystal cell controls a light transmittance in accordance with the pixel signal.
As a result, an electric field is formed between the pixel electrode 22 to which the pixel signal is applied via the TFT 30 and a common electrode (not shown), which exists usually on the other substrate. Liquid crystal molecules between the pixel electrode 22 and the common electrode rotate in response to the electric field due to the dielectric anisotropy of the liquid crystal molecules. The degree of the rotation control the light transmittance of the pixel area, thereby displaying a picture.
FIGS. 3A to 3F are sectional views illustrating a fabricating process of a liquid crystal display having polycrystalline silicon TFTs.
Firstly, an insulating material such as silicon oxide SiO2 is deposited on the entire lower substrate 1, thereby forming a buffer film 16, as shown in FIG. 3A. A gate metal layer is deposited on the entire surface of the lower substrate 1 with the buffer film 16 thereon, and then the gate metal layer is patterned by photolithography and etching processes including exposing and developing steps, thereby forming a gate electrode 6. The gate metal layer may be made of a metal including aluminum and aluminum/neodymium, etc.
A gate insulating material such as silicon oxide SiO2 is deposited on the entire surface of the lower substrate 1 with the gate electrode 6 thereon, thereby forming a gate insulating film 12 as shown in FIG. 3B. Then, an amorphous silicon film is deposited on the surface of the lower substrate 1 with the gate insulating film 12 thereon. Hydrogen contained in the deposited amorphous silicon film is removed by a dehydrogenating process, which generally includes a thermal treatment step. After the dehydrogenating process, the amorphous silicon layer is crystallized by a laser annealing, in which the amorphous silicon layer turns into a polycrystalline silicon layer. The polycrystalline silicon layer is patterned by photolithography and etching processes including exposing and developing steps, thereby forming an active layer 14.
A photo-resist is deposited on the entire surface of the active layer 14 with the lower substrate 1 thereon, and then is patterned by photolithography and etching processes including exposing and developing steps, thereby forming a photo-resist pattern. A predetermined amount of an impurity ion is injected into the area except for a channel area 14C of the active layer using the photo-resist pattern as a mask, thereby forming a source area 14S and a drain area 14D of the active layer as shown in FIG. 3C.
Herein, in case of a N-type TFT, n+ ions are injected into the active layer using a first photo-resist pattern as a mask, and n− ions are injected into the active layer using a second photo-resist pattern having a narrower width than the first photo-resist pattern as a mask. Accordingly, in the active layer of the N-type TFT, the area into which the n+and n− ions are not injected becomes a channel area, the area into which the n− ions are injected becomes an LDD area, and the area into which the n+ ions are injected becomes source and drain areas.
In case of a P-type TFT, p+ ions are injected into the active layer using a photo-resist pattern as a mask. Accordingly, in the active layer of P-type TFT, the area into which the p+ ions are not injected becomes a channel area, and the area into which the p+ ions are injected becomes source and drain areas.
A data metal layer is deposited on the entire surface of the lower substrate 1 with the channel area 14C, the source area 14S and the drain area 14D thereon, and then the data metal layer is patterned by photolithography and etching processes including exposing and developing steps, thereby forming a data line 4, source electrode 8 and a drain electrode 10, as shown in FIG. 3D.
An insulting material is deposited on the entire surface of the resultant lower substrate 1 with the data line 4, the source electrode 8 and the drain electrode 10 thereon, thereby forming a passivation film 18, as shown in FIG. 3E. Then, the passivation film 18 is patterned by photolithography and etching processes including exposing and developing steps, thereby forming a contact hole 20 exposing the drain electrode 10.
A transparent conductive material is deposited on the entire surface of the lower substrate 1 with the passivation film 18 thereon, and then the transparent conductive material is patterned by photolithography and etching processes including exposing and developing steps, thereby forming a pixel electrode 22, as shown in FIG. 3F. The pixel electrode 22 is electrically connected to the drain electrode 10 via the contact hole 20.
As described above, a fabricating method of the related art polycrystalline silicon TFT employs a six mask process, thereby complicating the fabricating process and increasing the fabrication costs. This is because each mask process includes a plurality of sub-processes, such as deposition, cleaning, photolithography, etching, photo-resist stripping and inspection. Accordingly, a fabricating method is needed and desirable that is simpler than the fabricating method of the related art allowing a reduced fabricating cost.
In addition, a laser annealing is mainly used to crystallize an amorphous silicon film into a polycrystalline silicon film. The laser annealing is a method to form a polycrystalline silicon film by irradiating a laser beam on an amorphous silicon film deposited on a substrate. In this method, laser energy of about tens or hundreds of ns is irradiated on an amorphous silicon film causing the amorphous silicon film to be in a melting condition, thereby forming a polycrystalline silicon. Although the crystallization method using the laser annealing has an advantage in that the crystallization can be performed at a low temperature, for example, at 400° C., the crystallization is not uniform. Further, it requires an expensive laser equipment, thereby decreasing productivity.